Article ID: 000082674 Content Type: Troubleshooting Last Reviewed: 09/25/2018

When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are the o_clk_rec_div66 and o_clk_pll_div66 clock rates reported incorrectly during timing analysis?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with Intel® Quartus® Prime software Pro version 18.0.1 and earlier, the output clock frequency of the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, signals o_clk_rec_div66 and o_clk_pll_div66 is reported incorrectly in timing analysis. The correct frequency for o_clk_rec_div66 is 156.25MHz and o_clk_pll_div66 is 390.625MHz.

    Resolution

    No workaround for this problem is available.

    This problem has been fixed starting in Intel® Quartus® Prime Pro software version 18.1.

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