Article ID: 000082670 Content Type: Troubleshooting Last Reviewed: 06/13/2018

When using the Intel® Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You may observe a correctable error assertion during the Recovery state when the Intel® Arria® 10 PCIE* IP core changes the speed from Gen3 x1/x2 to Gen1 or Gen2. The corretable error during the speed change does not indicate low link quality and can be ignored. 

    Resolution

    No workaround or fix is required for this problem. Once the error is cleared by system software, it should remain deasserted.   

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