Article ID: 000082664 Content Type: Install & Setup Last Reviewed: 01/17/2023

Why do I get fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP, where PTP and RSFEC options have been enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You might see Intel® Quartus® Prime Software fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP when PTP and RSFEC options have been enabled.

    This problem is due to incorrect Intel Quartus Prime Software fitter rules pertaining to channel placement checks when RSFEC and PTP are being used. The checks incorrectly restricted the odd RSFEC locations RSFEC_1 and RSFEC_4 which correspond to the PTP phase-locked loop (PLL) locations.

    For more information, refer to the E-Tile Channel Placement Tool.

    Resolution

    As a workaround, install the following patch for Intel® Quartus® Prime Software v18.1:

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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