Article ID: 000082664 Content Type: Troubleshooting Last Reviewed: 10/16/2018

Why do I get fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP, where PTP and RSFEC options have been enabled?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You may see Intel® Quartus® Prime fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP when PTP and RSFEC options have been enabled.

    This problem is due to incorrect Quartus fitter rules pertaining to channel placement checks when RSFEC and PTP are being used. The checks incorrectly restricted the odd RSFEC locations RSFEC_1 and RSFEC_4 which correspond to the PTP PLL locations.

    For further information please refer to the E-Tile Channel Placement Tool.

    Resolution

    As a work around, please install the patch below for Intel Quartus Prime v18.1.

    quartus-18.1-0.05-windows.exe

    quartus-18.1-0.05-linux.run

    quartus-18.1-0.05-readme.txt

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.

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