Why do I get fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP, where PTP and RSFEC options have been enabled?

You might see Intel® Quartus® Prime Software fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP when PTP and RSFEC options have been enabled.

This problem is due to incorrect Intel Quartus Prime Software fitter rules pertaining to channel placement checks when RSFEC and PTP are being used. The checks incorrectly restricted the odd RSFEC locations RSFEC_1 and RSFEC_4 which correspond to the PTP phase-locked loop (PLL) locations.

For more information, refer to the E-Tile Channel Placement Tool.

As a workaround, install the following patch for Intel® Quartus® Prime Software v18.1:

• quartus-18.1-0.05-windows.exe
• quartus-18.1-0.05-linux.run
• quartus-18.1-0.05-readme.txt

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Software.