Article ID: 000082607 Content Type: Troubleshooting Last Reviewed: 08/27/2014

Why does my Arria II GX design report minimum period violations on the JTAG clock?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a problem in the Quartus® II software, Arria® II GX designs may report minimum period violations on the JTAG clock. This problem is due to an incorrect timing model which specifies a minimum period of 100 ns instead of the actual limit of 30 ns.
Resolution If the period for your JTAG clock is greater than or equal to 30 ns, you may safely ignore this violation.

Related Products

This article applies to 1 products

Arria® II GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.