Article ID: 000082566 Content Type: Troubleshooting Last Reviewed: 09/02/2015

What should be considered to reduce Simultaneous Switching Noise (SSN) on a PCI interface implemented on my Cyclone series FPGA?

Environment

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Description

There are SSN considerations to make when the Address/Data (AD) bus on a target PCI interface  changes from output to high impedance (Hi-Z), on a Cyclone® series device.

For example, if a Cyclone series device acting as the target PCI device drives the AD bus from high to low (or low to high) and a short time after that (several nanoseconds), the output enable (OE) signal goes from high (output) to low( Hi-Z) the FPGA will appear to output a short pulse before disabling the output driver.

In this case, signals on the AD bus may ring with large amplitude because the AD bus has gone into a high impedance state immediately after a pulse injection.

If multiple AD signals near the clock input pin are ringing, this may cross-talk to the clock input pin and the target FPGA may capture the wrong clock edge.

 

Resolution

Here are two possible workarounds to avoid this.

 

1. Toggle the OE signal earlier so that OE goes low before the AD bus toggles.

2. Prevent the AD bus from toggling when OE goes from high to low.

Related Products

This article applies to 13 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® III FPGAs
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Cyclone® II FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® FPGAs
Cyclone® V E FPGA
Intel® MAX® 10 FPGAs
Cyclone® III LS FPGA
Cyclone® V SE SoC FPGA

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