Article ID: 000082561 Content Type: Troubleshooting Last Reviewed: 11/20/2015

Timing Violation for Arria 10 HDMI Design

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When you run the HDMI design for Arria 10 devices, the design may encounter timing violation within the dual-clock FIFO (DCFIFO) block. The DCFIFO block bypasses the HDMI video, audio, and auxiliary data from the receiver to the transmitter.

    The timing violation only occurs when you run the design in the Quartus Prime Pro Edition version 15.1.

    Resolution

    There is no workaround for this issue.

    This issue will be fixed in a future version of the HDMI IP core.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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