Article ID: 000082527 Content Type: Troubleshooting Last Reviewed: 06/18/2018

Why is the Intel® Stratix® 10 E-tile Hard IP for Ethernet (10G/25G) TX Timestamp error > 1 second?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem in Intel® Quartus® Prime Pro version 18.0 and earlier, the Intel® Stratix® 10 E-tile Hard IP for Ethernet (10G/25G) will occasionally issue a TX timestamp that is 1 second larger than expected. This causes an inaccurate error of 1 second in the TX timestamp.

    Resolution

    A possible work around to this problem would be to compare the TX timestamp against the time-of-day(ToD), and then subtract 1 second from it if the timestamp is 1 second larger than the ToD.

    This problem is scheduled to be fixed in the next release of the Intel® Quartus® Prime software.

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