Article ID: 000082525 Content Type: Troubleshooting Last Reviewed: 09/12/2012

ncelab: *E,CFEPLM : Foreign module port * of mode in must be associated with port/signal of entity/component ALTPCIE_AV_HIP_AST_HWTCL

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error in elaboration process of ncsim simulation with PCIe VHDL simulation code for Arria V Hard IP due to Quartus II software problem.

    To prevent this error, you should generate Arria V PCIe simulation model in Verilog language format instead of VHDL format.

    This issue is scheduled to be fixed in a future release of Quartus II software. 

    Related Products

    This article applies to 2 products

    Arria® V GT FPGA
    Arria® V GX FPGA

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