Article ID: 000082512 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Are there any known issues with the Stratix V Low Latency PHY when using an embedded reset controller in Quartus II software version 12.0?

Environment

  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
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    Description

    Yes, there is a known bug in the Stratix® V Low Latency PHY when using an embedded reset controller in Quartus® II software version 12.0.

    • When configured for a bonded interface, each channel has its own reset.
    • When configured for a non-bonded interface, all channels share a reset.

    The correct behaviour should be

    • When configured for a bonded interface, all channels share a reset.
    • When configured for a non-bonded interface, each channel has its own reset.
    Resolution To work around this problem, upgrade to Quartus II Software Version 12.0SP1.

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