Description
This error message is found in the Quartus II software versions 2.1 and above. It indicates that a node in the design has multiple assignments because the net has more than one driver in the design. The second error indicates a line number at the end of a design block where one of the assignments is made. You should correct your Verilog HDL or VHDL code so that you do not make multiple assignments or drivers to the same signal.
The Quartus II software versions lower than 2.1 did not produce an error for these kind of illegal multiple assignments. Therefore, you may see this error with older code that compiled successfully in a version prior to 2.1 because the code may have relied on the Compiler not to give an error for these cases. Multiple assignments to the same signal, however, are not supported in the Verilog HDL or VHDL languages, and other third-party synthesis tools will also produce an error for this type of coding. You must correct your HDL code to fix this problem and eliminate the error message during compilation.