Are there any issues with the calibration process when using the Altmemphy or the DDR/DDR2 High Performance controller in the Stratix II devices in Quartus II software 7.2 and earlier versions?

Stratix® II scandone Signal Can Be Stuck High During PLL Reconfiguration.

Three cases exist where PLL reconfiguration may cause the scandone signal to become stuck high as described in the Stratix II FPGA Family Errata Sheet (PDF).

You might not be able to complete the Initial Calibration Sequence when using Altmemphy or DDR/DDR2 High Performance Controller.

Altmemphy uses PLL phase shift stepping and is subject to scandone stuck high issue. The PHY reconfigures the phase shift of the M or the C[5..0] counters using the phase-shift stepping feature as defined in case 3 in the Stratix II errata. The phase stepping in the Altmemphy and the DDR/DDR2 High Performance controller relied on scandone in the Quartus® II software and IP version 7.2 and earlier. If scandone gets stuck high, the PHY will hang during the initial calibration sequence.

This impacts Stratix II, Stratix II GX, HardCopy® II and Arria™ GX devices.

This does not impact Cyclone® II, Cyclone III, Stratix III or Stratix IV devices.

The workaround for this issue has been implemented in the IP in Quartus II software version 7.2SP1. It is recommended that you regenerate the IP using 7.2SP1 or the latest version of Quartus II software.