Article ID: 000082430 Content Type: Error Messages Last Reviewed: 08/03/2023

Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_arriav.cpp, Line: 575 Illegal setting: (side, triplet, channel) = (1,1,1): (iqtxrxclk_a_sel, iqtxrxclk_b_sel) =(4,1)

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software, you may see this error when compiling an Arria® V design using Transceivers. This is the result of TX or RX clock routing congestion.

Resolution

To work around this problem, try using the txclkout and rxclkout ports from a different channel to alleviate the congestion.

 

Related Products

This article applies to 1 products

Arria® V FPGAs and SoC FPGAs

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