Article ID: 000082421 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the PCIe I/O BAR size is limited to 4kBytes in the IP Compiler for PCI Express Megawizard GUI when configured as Legacy Endpoint?

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Description According to PCI® 3.0 base spec, I/O space must not consume more than 256 bytes per I/O Base Address register and the upper 16 bits of I/O Base Address registers are hardwired to zero for devices intended for 16 bit I/O system.  Since I/O space is usually used for controlling peripheral as single dword accesses, users do not typically need to allocate a large I/O memory map for this purpose.

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Stratix® IV GX FPGA

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