Article ID: 000082376 Content Type: Troubleshooting Last Reviewed: 01/17/2023

Why do I see marginal hold time failures when compiling the JESD204B IP targeting Intel® Stratix® 10 L-tile production devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to different placement and fitting of the JESD204B IP compiled across different seeds in the Intel® Quartus® Prime Pro Edition Software, you might see marginal hold time failures for interfaces with data rates rates at 13.5 Gbps and 15 Gbps or above. You might see this problem when targetting Intel® Stratix® 10 L-tile production devices with a core speed grade of -2 or -1.

     

    Resolution

    Use Design Space Explorer to compare compilation results with different seeds and select the seed that passes timing.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.