Article ID: 000082375 Content Type: Troubleshooting Last Reviewed: 08/09/2018

Why can't I read from the transceiver reconfiguration bus of my Intel® Stratix® 10 Low Latency 100Gbps Ethernet IP core in simulation?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In order to read from the transceiver reconfiguration bus of the Intel® Stratix® 10 Low Latency 100Gbps Ethernet Intel® FPGA IP core in simulation, check the "Enable ADME" dialog box in the IP core GUI. 

    Resolution

    There is no workaround for this issue. 

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