Article ID: 000082373 Content Type: Troubleshooting Last Reviewed: 11/14/2018

Why might my Intel® Quartus® Prime software version 18.1 and earlier compilation flow get stuck in the Route stage for several hours when fast pipeline registers are enabled in the Intel® Stratix® 10 TX or MX device E-Tile Native PHY IP?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime software version 18.1 and earlier, the compilation flow may get stuck in the Route stage for several hours when the fast pipeline registers are enabled in the Intel Stratix 10 TX or MX device E-Tile Native PHY IP. The compilation flow may eventually run to completion with several hold time violations on the core to periphery and periphery to core paths. 

    Resolution

    To work around this problem, uncheck the "Enable TX fast pipeline registers" and "Enable RX fast pipeline registers" option on the "Core Interface" tab of the Intel Stratix 10 TX or MX device E-Tile Native PHY IP.

    This probelm will be fixed in a future version of the Quartus Prime software.

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