Article ID: 000082372 Content Type: Troubleshooting Last Reviewed: 05/10/2018

Why do I see hold time violations when using the 10GBASE-KR PHY Intel® Stratix® 10 FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
  • 1G 10GbE and 10GBASE-KR PHY Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with the 10GBASE-KY PHY Intel® Stratix® 10 FPGA IP you may see minor hold time violations in the 10GBASE-KR IP during compilation.

    Resolution

    A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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