Article ID: 000082370 Content Type: Troubleshooting Last Reviewed: 08/15/2018

Why does the Intel® Quartus® Prime Pro compilation show warning message: "Ignored set_max_skew at alt_e2550_ptp_fifo_top.sdc" when compiling FPGA design with 25G Ethernet Intel® FPGA IP ?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the 25G Ethernet Intel® FPGA IP v18.0 and earlier version, Intel® Quartus® Prime design compilation will show the warning message: "Ignored set_max_skew at alt_e2550_ptp_fifo_top.sdc" when implemented in VHDL and with multiple instances of the 25G Ethernet Intel FPGA IP in the design.  

    Resolution

    To work around this problem:

    In the file alt_e2550_ptp_fifo_top.sdc change:

    FROM:

    set inst_list [query_collection -list -all $inst]       

             foreach each_inst $inst_list {

    TO:

    foreach_in_collection each_inst_tmp $inst {       

             set each_inst [get_node_info -name $each_inst_tmp]

     

    This problem has been fixed starting with Intel® Quartus® Prime Pro version 18.0.1

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.