Article ID: 000082358 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues with the global clock network connections table in the PLL chapter of the Cyclone II device Handbook?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Table 79 of the PLL chapter of the Cyclone II device Handbook has incorrect LVDSCLK numbering.

The correct mapping between the CLK(x) and LVDSCLK(x)p/n pins is as shown below:


CLK0, LVDSCLK0p
CLK1, LVDSCLK0n
CLK2, LVDSCLK1p
CLK3, LVDSCLK1n
CLK4, LVDSCLK2p
CLK5, LVDSCLK2n
CLK6, LVDSCLK3p
CLK7, LVDSCLK3n
CLK8, LVDSCLK4n
CLK9, LVDSCLK4p
CLK10, LVDSCLK5n
CLK11, LVDSCLK5p
CLK12, LVDSCLK6n
CLK13, LVDSCLK6p
CLK14, LVDSCLK7n
CLK15, LVDSCLK7p

This will be fixed in a future version of the Cyclone II device Handbook.

Related Products

This article applies to 1 products

Cyclone® II FPGA

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