Article ID: 000082355 Content Type: Troubleshooting Last Reviewed: 05/29/2014

Why does Configuration via Protocol (CvP) fail to initiate core image update at PCIe Gen1 x1 in Cyclon V or Arria V?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1 update 4 and earlier, the CvP may fail to initiate core image update showing time out error at PCI Express® Gen 1 x1 in Cyclone® V or Arria® V.  The problem affects core image update in both the CvP Update mode and the CvP initialization mode.  It does not affect the first core image configuration right after the periphery image configuration in CvP initialization mode.  The problem doesn't happen in PCIe Gen 1 x4 or x8.

    Resolution

    To avoid this problem, complete following steps:

    1. Search for the Reconfiguration Controller instance named alt_xcvr_reconfig and comment out the entire reconfig_controller in your design.
    2. Add the 5 lines of  shown in Verilog HDL below after the commented out instance, alt_xcvr_reconfig:

      wire [69:0] reconfig_to_xcvr_bus = {25\'h0, 1\'b1, 44\'h0};
      assign pcie_reconfig_driver_0_reconfig_mgmt_waitrequest = 1\'b0;
      assign pcie_reconfig_driver_0_reconfig_mgmt_readdata = 32\'h0;
      assign alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy = 1\'b0;
      assign alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcv r = { 2 {reconfig_to_xcvr_bus}};

     

     This problem is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 4 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA

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