Altera has identified the following issue in Quartus® II 9.0SP2 for Stratix® IV transceivers Basic (PMA Direct) mode configurations.
Software Timing models are preliminary, which may result in timing violations for designs using Basic (PMA Direct) mode configurations. To work around the issue, follow the design guidelines below.
a) To meet the setup and hold time requirements on the receiver-FPGA fabric interface,
capture receive parallel data (rx_dataout) using the positive edge of recovered clock (rx_clkout) and add the following multi-cycle constraint in the SDC file.
set_multicycle_path -setup -from [get_registers rx_data_reg*] 0
set_multicycle_path -hold -from [get_registers rx_data_reg*] 0
rx_data_reg are the registers used to capture the RX data from the rx_dataout port of the RX PMA in the FPGA core.
b) If your compiled design using this procedure shows timing violations (depends on transceiver data rate and logic utilization), use the negative edge of rx_clkout to clock the receive parallel data and remove the above mentioned multi-cycle constraints from the SDC file. For additional information please refer the Application Note AN580 -Achieving timing closure in Basic (PMA Direct) modes (PDF).