Article ID: 000082270 Content Type: Troubleshooting Last Reviewed: 11/20/2013

Why is the RTL simulation result for PLL phase shifts not correct for the ALTPLL megafunction Cyclone III and Cyclone IV devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The RTL simulation results may show incorrect phase shifts for ALTPLL megafunction generated files depending on your PLL settings.  This affects ALTPLL megafunctions generated for VHDL and Verilog in Cyclone® III and Cyclone IV devices.

    This issue will also affect RTL simulations when using the ALTLVDS megafunction since it also uses clocks from the ALTPLL megafunction. 

    Resolution

    In order to obtain the correct phase shift result from the simuation, you can use the post-fit simulation model (.vho file). 

    Related Products

    This article applies to 3 products

    Cyclone® III FPGAs
    Cyclone® III LS FPGA
    Cyclone® IV E FPGA

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