Description
The RTL simulation results may show incorrect phase shifts for ALTPLL megafunction generated files depending on your PLL settings. This affects ALTPLL megafunctions generated for VHDL and Verilog in Cyclone® III and Cyclone IV devices.
This issue will also affect RTL simulations when using the ALTLVDS megafunction since it also uses clocks from the ALTPLL megafunction.
Resolution
In order to obtain the correct phase shift result from the simuation, you can use the post-fit simulation model (.vho file).