CPRI IP Core RE Slave May Start Up or Reset in Master Clocking Mode

The value in the CPRI IP core CPRI_CONFIG register operation_mode field specifies whether the IP core is in master clocking mode or in slave clocking mode. The reset value of this register field should be the value you specify for the Operation mode parameter in the CPRI parameter editor.

However, in both simulation and hardware, when a CPRI IP core in slave clocking mode resets or starts up, this register field may have the value of 0, erroneously specifying master clocking mode. The incorrect value causes the IP core to attempt to operate in the wrong clocking mode.

This issue affects the following CPRI IP core instances:

• Instances that target an Arria II, Cyclone IV, or Stratix IV device.
• Instances that target an Arria V GZ or Stratix V device and are configured with a CPRI line rate of 4.9152 Gbps or lower.
• Instances that target an Arria V GZ, Arria V GT, or Cyclone V device and are configured with a CPRI line rate of 3.072 Gbps or lower.

To work around this issue, ensure that you write the value of 1 to this register field during IP core start-up and immediately following reset.

This issue is fixed in version 14.0 of the CPRI MegaCore function.