Article ID: 000082226 Content Type: Troubleshooting Last Reviewed: 10/29/2018

Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem with the write address decoding for the Intel® Arria® 10 PCI Express* Hard IP, you may fail to clear the lane error status register after writing ‘1’ to this register.

    Resolution

    To work around this problem, write a ‘1’ to link control 3 register (Offset 04h) located in the Secondary PCI Express* Extended Capability. This register will be set and the lane error status register will be cleared.

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