Warning (16817): Verilog HDL warning at altera_xcvr_*_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_*_reconfig_parameters package

If your design contains multiple JESD204B IPs with different configurations, you may see the following warning in Intel® Quartus® Prime Pro software version 15.1 or later during Analysis and Synthesis stage.

When targetting Intel Stratix® 10 devices:

Warning (16817): Verilog HDL warning at altera_xcvr_rcfg_10_reconfig_parameters.sv: overwriting previous definition of module altera_xcvr_rcfg_10_reconfig_parameters

When targetting Intel Arria® 10 or Intel Cyclone® 10 GX devices:

Warning (16817): Verilog HDL warning at altera_xcvr_native_a10_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_native_a10_reconfig_parameters package

If your design does not rely on the *_reconfig_parameters.sv package files for performing transceiver reconfiguration, it is safe to ignore the warning.

If your design must include the reconfiguration packages, ensure the uniqueness of each of the packages by renaming the packages. 

For example, a design that contains two simplex RX interfaces with different data rates, assign a unique name by changing the package module from:

package altera_xcvr_native_a10_reconfig_parameters;

To:

package altera_xcvr_native_a10_reconfig_parameters_inst1;

In the first instance of RX, and changing to another unique name:

package altera_xcvr_native_a10_reconfig_parameters_inst2;

In the second instance of RX. Then, import those packages in your design per your design requirements.

This problem will be fixed in a future version of the Intel Quartus Prime Pro software.