Are the RS-FEC Alignment Markers correct when using the 25G Ethernet FPGA IP for Intel® Arria® 10 or Intel® Stratix® 10 devices?

When using the 25G Ethernet FPGA IP for Intel® Arria® 10 or Intel® Stratix® 10 devices, the optional RS-FEC alignment markers do not conform to the final version of the specification.

The 25G - 50G Spec 3.2.1.1.2 25G PCS sublayer operation for links that use RS-FEC states that the Alignment markers should be:

[256] = 0

[255:0] ='{

0xC1, 0x68, 0x21, 0x33, 0x3E, 0x97, 0xDE, 0xCC, // AM0 (PCS lane 0)

0xF0, 0xC4, 0xE6, 0x33, 0x0F, 0x3B, 0x19, 0xCC, // AM1 (PCS lane 1)

0xC5, 0x65, 0x9B, 0x33, 0x3A, 0x9A, 0x64, 0xCC, // AM2 (PCS lane 2)

0xA2, 0x79, 0x3D, 0x33, 0x5D, 0x86, 0xC2, 0xCC}; // AM3 (PCS lane 3)

The 25G Ethernet IP sends:

[256] = 1

[255:0] ='{

0xC1, 0x68, 0x21, 0x33, 0x3E, 0x97, 0xDE, 0xCC, // AM0 (PCS lane 0)

0xF0, 0xC4, 0xE6, 0x00, 0x0F, 0x3B, 0x19, 0xFF, // AM1 (PCS lane 1)

0xC5, 0x65, 0x9B, 0x00, 0x3A, 0x9A, 0x64, 0xFF, // AM2 (PCS lane 2)

0xA2, 0x79, 0x3D, 0x00, 0x5D, 0x86, 0xC2, 0xFF}; // AM3 (PCS lane 3)

Alignment markers AM1, AM2 and AM3 use incorrect BIP3 and BIP7 values of 0x00 and 0xFF. 0x33 and 0xCC should be used as in AM0.

As stated in the user guide, this is due to the 25G Ethernet IP conforming to the Draft 1.6 version of the 25G & 50G Ethernet Specification.

No workaround to this problem exists.

This problem has been fixed starting in version 19.1 of the Intel® Quartus® Prime Design Software.