Article ID: 000082220 Content Type: Product Information & Documentation Last Reviewed: 09/26/2018

How do I determine if there is an "RX completion buffer overflow" with the Intel® Arria® 10 or the Intel® Cyclone® 10 PCIe* Avalon®-MM DMA IP core if Platform Designer does not allow the users to enable this option?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    The Intel® Arria® 10 or the Intel® Cyclone® 10 PCIe* Avalon-MM® DMA version of the IP core does not allow the users to enable the "RX completion buffer overflow" option.  This is because the DMA engine ensures that it will not request completions that exceed the available buffer size.

    Moreover, per the PCI-SIG specification, the endpoint needs to advertise infinite completion buffer space to the root port.

    Resolution

    The "RX completion buffer overflow" option is not allowed to be enabled for The Intel® Arria® 10 or the Intel® Cyclone® 10 PCIe* Avalon-MM® DMA version of the IP core, and it should be left unchecked.

     

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