Article ID: 000082219 Content Type: Troubleshooting Last Reviewed: 02/13/2013

Incorrect Description of edgecapture Bit Clearing

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

In the PIO Core chapter of the Embedded Peripherals IP User Guide, a footnote to Table 10-2 incorrectly states “Writing any value to edgecapture clears all bits to 0.” This statement is only true if the Enable bit-clearing for edge capture register option is turned off.

Resolution

The footnote should read as follows:

If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit.

Related Products

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Intel® Programmable Devices

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