There are a number of different possibilities when trying to simultaneously read and write to the same address in dual-port RAM in the Quartus® II software and the MAX PLUS® II software.
When the output port of the RAM is unregistered, one of the following situations will occur:
Case 1: The read clock's frequency is greater than 2x the write clock's frequency. The write clock has not written the data at this point; therefore, the read clock accesses the old data value.
Case 2: Dual-port RAM uses the same clock for reading and writing. The newly written data appears at the output (tEABDD), after the falling edge of the clock. At slower clock frequencies, the old data value can appear shortly after the rising edge of the clock followed by the newly written data, which appears at tEABDD after the falling edge.
When the output port of the RAM is registered, the following conditions hold:
Case 1: The read clock is very fast (frequency > 1/tEABDD). The q output reads the old data value.
Case 2: Dual-port RAM uses the same clock for reading and writing. The q output reads the newly written data value.
Case 3: The read and write clocks are unrelated, and the read clock has a frequency less than 1/tEABDD. The q output reads the newly written data value.
 | tEABDD is the EAB data-in to data-out valid delay for FLEX® 10K devices and tESBDD is the ESB data-in-data-out valid delay for APEXTM 20K devices; these parameters are specified in the appropriate device family data sheet. |