Article ID: 000082194 Content Type: Troubleshooting Last Reviewed: 02/08/2012

rx_oc_busy Port Is Not A Top-Level Signal

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

The 10GBase-R PHY IP Core chapter of the Altera Transceiver PHY IP Core User Guide describes the rx_oc_busy signal as a top-level signal of the IP core; however, this signal is now included in the reconfiguration bus.

Resolution

This issue is fixed in version 11.1 SP2 of the Altera Transceiver PHY IP Core User Guide.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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