Article ID: 000082145 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is there no activity on DQ and DQS signal before ctl_cal_success signal goes high when simulating DDR3 High Performance Controller created in Quartus II version 7.2SP3?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For Quartus® II software and IP version 7.2SP3, there is no calibration performed in the simulation mode, therefore you will not see any activity on DQ abd DQS signals before ctl_cal_success signal goes high.

Calibration support in simulation will be added in the future version of the Quartus II software and the IP.

Related Products

This article applies to 1 products

Stratix® III FPGAs

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