Article ID: 000082131 Content Type: Troubleshooting Last Reviewed: 05/06/2014

Why does my Stratix V, Arria V or Cyclone V device fail to enter user mode when configured over JTAG, when I have a CvP mode enabled in my project?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description A Stratix® V, Arria V or Cyclone V device may fail to enter user mode when configured over JTAG, if the .sof is generated from a Quartus® II project where a Configuration via Protocol (CvP) mode is enabled. This is because when you have CvP mode enabled and when you configure the FPGA over JTAG, it would then be necassary to write to the CvP Mode Control registers in the PCIe IP (via the PCIe link) after configuration is complete, to allow the device to enter user mode.
Resolution To configure the device over JTAG, recompile the project with the CvP mode disabled, to generate a new .sof.

Related Products

This article applies to 12 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA

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