Article ID: 000082090 Content Type: Troubleshooting Last Reviewed: 10/11/2018

Why do CSR read/write accesses to the H-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Core take more than 100 Avalon®-MM clock cycles (reconfig_clk)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    CSR read/write accesses to the H-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Core take more than 100 Avalon®-MM clock cycles (reconfig_clk) as shown in simulation.

    This is the expected behavior due to the 8-bit CSR interface on the H-tile Hard IP Ethernet Intel Stratix 10 FPGA Core. Each user Avalon®-MM 32-bit interface read/write results in 32-bit to 8-bit bus data width conversion logic which causes the extra access latency.


    Note:  The Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core (soft IP) CSR interface does not have this extra latency.

    Resolution

    Not Applicable

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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