Article ID: 000082089 Content Type: Troubleshooting Last Reviewed: 10/30/2018

Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1, you may observe a minimum pulse width timing violation information message during compilation.

    Resolution

    This message can be safely ignored.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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