Article ID: 000082088 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my DDR3 High Performance controller with ECC enabled issue read-modify-write (RMW) commands with the wrong data?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The DDR3 SDRAM High Performance Controller MegaCore in Quartus® II software versions 9.0 SP2 and earlier issues read-modify-write (RMW) commands with incorrect data when the ECC feature is enabled. This controller problem can result in invalid data being written into the memory device and cause functional failures.

Patch 2.06 is available to fix this problem in the Quartus II software version 9.0 SP2. If you are using version 9.0 or 9.0 SP1, first download and install the Quartus II Software version 9.0 Service Pack 2. Download the appropriate Quartus II software version 9.0 SP2 patch 2.06 from the following links:

To fix the problem, regenerate and recompile all instances of the DDR3 SDRAM High Performance Controller MegaCore in your design using the updated Quartus II software.

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.