Article ID: 000082081 Content Type: Troubleshooting Last Reviewed: 11/29/2016

40-100GbE IP Core Might Provide Incorrect Parity Error Information in MAC_HW_ERR Register Bit 5

Environment

    Intel® Quartus® Prime Pro Edition
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Critical Issue

Description

The MAC_HW_ERR register (offset 0x120) field in bit 5 should indicate the presence or absence of a parity error in the DOE command FIFO buffer section. However, this bit might have an incorrect value.

Resolution

This issue has no workaround. Ensure you do not rely on the value in bit 5 of the MAC_HW_ERR register in versions 15.0 and earlier of the 40-100GbE IP core.

This issue is fixed in version 15.1 of the 40-100GbE IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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