Why do I see a spurious readdatavalid pulse from the Avalon MM Clock Crossing Bridge when the master reset is asserted?

You may see an incorrect readdatavalid pulse at the Avalon® MM slave interface when the Avalon MM master interface reset is asserted on the Avalon MM Clock Crossing Bridge.

A clock crossing bridge is inferred by Qsys when an Avalon MM master is connected to an Avalon MM slave. The clocks and the resets for the two interfaces are different.

To avoid this situation, ensure that the reset for both ports of the Avalon MM Clock Crossing Bridge are from the same source so that they cannot be independently asserted.

The reset scheme of the Avalon MM Clock Crossing Bridge is scheduled to be enhanced in a future version of the Quartus® II software