Article ID: 000082009 Content Type: Troubleshooting Last Reviewed: 04/02/2014

What is the maximum payload size supported in Stratix V Hard IP for PCI Express?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a documentation error, the table Dynamically Reconfigurable Registers in the Hard IP Implementation of the Stratix® V Hard IP for PCI Express® User Guide shows a 4096 byte maximum payload while other tables show 2048 bytes as the maximum.
Resolution

The correct maximum payload size is 2048 bytes.

This will be corrected in a future version of the User Guide.

Related Products

This article applies to 3 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.