Article ID: 000081997 Content Type: Troubleshooting Last Reviewed: 01/07/2014

What are the typical rules for sharing a Tx PLL between multiple transceiver instances on Stratix V, Arria V, and Cyclone V transceiver devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The typical rules for sharing a Tx PLL between multiple transceiver instances on Stratix® V, Arria® V, and Cyclone® V transceiver devices are as follows.

  • All transceiver instances intended to share a Tx PLL must have a common refclk input.
  • All transceiver instances intended to share a Tx PLL must have a common Tx PLL VCO (base data rate) frequency.
  • All transceiver instances intended to share a Tx PLL must have common Tx PLL reset or power down inputs.
  • All transceiver instances intended to share a Tx PLL must have common reconfiguration controller.
  • Sharing Tx PLLs for designs that also implement dynamic reconfiguration require a Quartus® II XCVR_TX_PLL_RECONFIG_GROUP QSF assignment for each transceiver sharing the Tx PLL.

Failure to adhere to the above requirements may result in a Quartus® II No Fit error.

You can refer to the device specific handbook or PHY IP Userguide for further information.

Related Products

This article applies to 12 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA

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