Article ID: 000081974 Content Type: Error Messages Last Reviewed: 11/15/2015

Error: (vsim-3058) The width (1) of Verilog port 'scaninb' does not match the array length (8) of its VHDL connection

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error if you generate Altera® Multiply Adder in Quartus® II v13.0. 

    Resolution

    This issue has been fixed in Quartus II software version 14.0 and later.

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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