Article ID: 000081957 Content Type: Troubleshooting Last Reviewed: 03/15/2019

Why does the rx_digitalreset and tx_digitalreset signals of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core cannot connect to the Transceiver PHY reset controller Intel® FPGA IP in Platform Designer?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Arria® V FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem with Intel® Quartus® Prime software, the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP has incorrect type of interface for rx_digitalreset and tx_digitalreset signals, therefore you cannot connect these two signals to the Transceiver PHY reset controller Intel FPGA IP at Platform Designer. The correct type of interface for rx_digitalreset and tx_digitalreset signals are conduit NOT reset.

    Resolution

    Export the rx_digitalreset and tx_digitalreset signals from Platfrom Designer and manually connect at RTL. This problem will be fixed in a future version of Intel Quartus Prime software.

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