Article ID: 000081942 Content Type: Troubleshooting Last Reviewed: 03/29/2023

Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface?

Environment

    Quartus® II Subscription Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The use of the afi_rlat signal is not supported for PHY-Only designs.

Resolution

The workaround is to use the afi_rdata_valid signal to determine when valid read data is available.

For more information, refer to the External Memory Interface Handbook.

Related Products

This article applies to 17 products

Cyclone® V SX SoC FPGA
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Arria® V ST SoC FPGA
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