How do I pack registers into the I/O region if they are part of LogicLock regions?

Due to a problem in the Quartus® II software version 10.1 and later, Fast Input Register, Fast Output Register, Fast Output Enable Register and Fast OCT Register assignments may be ignored if the following conditions are true:

• The registers that the assignments apply to are included in a LogicLock™ region
• The LogicLock region does not cover the the I/O region those registers connect to

Earlier versions of the Quartus II software recognized these assignments regardless of whether the affected registers were included in LogicLock regions.

To work around this problem, use one of the following methods:

• Ensure that registers with these assignments are not contained in any LogicLock region.
• Enlarge the LogicLock region to include the I/O region that the registers connect to.
• If enlarging the LogicLock region is not feasible, create a new LogicLock region at the top level of your design. Assign the affected registers as members of this LogicLock region and place the LogicLock region in the I/O region that the registers connect to. The LogicLock region should have its Reserved property turned off.

This problem is fixed beginning with the Quartus II software version 12.0.