Article ID: 000081888 Content Type: Error Messages Last Reviewed: 12/21/2022

Error (175001): Could not place path required to route a signal from PLD core to the I/O pin

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see this error in the Quartus® II Software versions 13.0 and 13.1 when using Arria® V or Cyclone® V SoCs. This error occurs when you use Hard Processor System (HPS) I/O pins and instantiate an ALTLVDS Intel® FPGA IP in the FPGA design.

    This is not a valid error; there are no resource dependencies between the HPS I/O pins and the FPGA I/O pins.

    Resolution

    Download the following patch to fix this error for the Quartus II software version 13.1:

     

    Related Products

    This article applies to 4 products

    Arria® V ST SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA

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