Article ID: 000081839 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I merge PLLs from two controllers to allow the controllers running on the same system clock and sit on the same Avalon bus without any additional bridging logic for Stratix II device?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Generate the two High Performance Controller IP cores using the Quartus software version 8.1 in the usual way.  Instantiate both cores together in a parent module. 

     

    The easiest method may be to edit the existing <core1_ddr2_hp>_example_top.v file for one controller.

    The second core instance needs to have an additional phy_clk_in input routed through its design hierarchy, which is then connected to the phy_clk from the first core.

     

    The edits which need to be made are:

    clock_sharing_ example_top.v

    Instantiate core2_ddr2_hp. Create a phy_clk_in port and connect to the  phy_clk of the first controller.

    <core2_ddr2_hp>.v

     

    1. Add the phy_clk_in input to the module I/O in module declaration section

    2. Create a new phy_clk_in input on the <core2_ddr2_hp>_controller_phy instance and connect to phy_clk_in.

    <core2_ddr2_hp>_controller_phy.v

     

    1. Add the phy_clk_in input to the module I/O in module declaration section

    2. Edit the clk input on the <core2_ddr2_hp>_auk_ddr_hp_controller_wrapper instance from phy_clk to phy_clk_in

    3. Edit in the new phy_clk_in input on the <core2_ddr2_hp>_phy instance and connect to phy_clk_in.

    <core2_ddr2_hp>_phy.v

     

    1. Add the phy_clk_in input to the module I/O in module declaration section

    2. Create a new phy_clk_in input on the <core2_ddr2_hp>_phy_alt_mem_phy instance and connect to it.

    <core2_ddr2_hp>_phy_alt_mem_phy.v

     

    1. Add the phy_clk_in input to the top level module I/O in module declaration section

    2. Edit in a new phy_clk_in input on the <core2_ddr2_hp>_phy_alt_mem_phy_clk_reset instance (instance to be found around line 924). 

    3. Edit the <core2_ddr2_hp>_phy_alt_mem_phy_clk_reset module declaration (declaration to be found around line 1472) to add the phy_clk_in input to the module I/O.

    4. Within the <core2_ddr2_hp>_phy_alt_mem_phy_clk_reset module declaration, locate either the full-rate or half-rate <core2_ddr2_hp>_phy_alt_mem_phy_pll instance, according to your configuration (instances to be found from around line 2278)

    For half-rate, delete the phy_clk_1x connection to the “c0” port and add an assign statement, just below the half_rate_clk assignment, which reads “assign phy_clk_1x = phy_clk_in”.

    For full-rate edit the assign phy_clk_1x statement, replace mem_clk_2x with phy_clk_in.

     

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs

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