EMIF Debug Toolkit Reports Margin Larger than Bit Period

This problem affects DDR2, DDR3, LPDDR2, QDR II, RLDRAM II, and RLDRAM 3 products.

The EMIF Debug Toolkit reports calibration margin greater than the memory interface bit period. This situation occurs because the delay chain step size reported in the toolkit is larger than the actual delay chain step size. The margins, in terms of the number of delay taps (which you can calculate by dividing the margin by the delay chain step size), are still correct.

The workaround for this issue is to manually derate the margin reported in the toolkit by 20 percent.

This issue will be fixed in a future release.