Article ID: 000081805 Content Type: Troubleshooting Last Reviewed: 10/10/2014

Cyclone® IV Device Handbook: Known Issues

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Issue 236435: Volume 1, Chapter 11, Power Requirements for Cyclone IV Devices, Version 1.3

In Table 11.1, note 3 states that “Device package F484 of EP4CGX30 have four VCC_CLKIN dedicated clock input I/O bank located at banks 3A, 3B, 8A, and 8B”.

This is not correct. The EP4CGX30F484 does not have I/O bank 8B, so it only has three VCC_CLKIN dedicated clock inputs which hare located in banks 3A, 3B, and 8A.

Issue 218194: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.8

Note 2 states that the 10uA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.

It should state that the 10uA I/O leakage current limit is applicable when the internal clamping diode is either enabled or disabled, and is reverse biased. A higher current can be observed when the diode is forward biased.

Issue 137998: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.7

Table 1-25 shows the PLL specifications for Cyclone IV devices. Note 1 indicates the specifications apply to both general purpose PLLs (GPLL) and multipurpose PLLs (MPLL). This table is incomplete. MPLLs support a VCO operating range from 600 to 1600MHz in the following Cyclone IV GX devices: EP4CGX30*, EP4CGX50, EP4CGX110, EP4CGX150.

* Applies to the F23 package only.

Issue 131091: Cyclone® IV Devices Datasheet, Version 1.7

Note 5 for Table 1-3: Recommended Operating Conditions for Cyclone IV E Devices instructs you to select C8 as the target device when designing for an I7 device in the Quartus® II software. This instruction is incorrect. In the Quartus® II software, targeting a C8 device is not necessary because there is option to set 125 °C as the maximum temperature in the Junction temperature range on the Temperature page of the Settings dialog box.

Issue 119744: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.6

In Table 8-17 and 8-18 it shows that DATA[0] as a dedicated pin "Yes" but should be a "-" as the DATA0 pin will be available as a user I/O pin after configuration in Active Serial (AS) mode but not in Passive Serial (PS) or Fast Passive Parallel (FPP) modes.

Table 8-19 will also be updated to reflect this.

Issue 119386: Volume 1, Chapter 11, Power Requirements for Cyclone IV Devices, Version 1.2

Table 11-1 says in note 4 VCC_CLKIN for I/O banks 3A and 8A only supports 2.5V.  This is not correct, when not used for HSSI refclk, the clock input pins in banks 3A and 8A support 1.2 V/ 1.5 V/ 1.8 V/ 2.5 V/ 3.0 V/ 3.3V voltages.

Issue 66850: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.4

Notes to Table 1 of Table 8-17 and Note 4 of Table 8-18 state that "The CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain output in the CRC Error Detection tab of the Device and Pin Options dialog box" which is incorrect.

The Notes to Table will be updated to state "Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled in the Quartus II software from the Error Detection CRC tab of the Device and Pin Options dialog box.

When using this pin, connect it to an external 10K-ohm pull-up resistor to an acceptable voltage that satisfies the input voltage of the receiving device."

Issue 35742:  Volume-2, Chapter 1, Cyclone IV Transceivers Architecture, Version 3.3

In the Transceiver Clocking Architecture section, note (1) under Figure 1-27 states, "VICM can be sourced from the 2.5-V supply with a voltage divider circuit (typically two 1-kohm resistors)." That would make the VICM to be 1.25V.

However, in the Cyclone IV Device Datasheet, the specification of VICM (AC coupled) for the reference clock input is 1.1V -5, which is correct information.

Figure 1-27 will be updated in a future version of the handbook.

Issue 46239:  Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.5

The pin capacitance in Table 1-11 in the Cyclone IV Datasheet applies to FBGA, UBGA, and MBGA packages.

Issue 379673: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.3

The correct frequency for CLKUSR in Cyclone IV devices is 40MHz during user mode.

In the Cyclone IV handbook there is a section called "Overriding Internal Oscillator" which states that CLKUSR is 80MHz, this is incorrect and will be fixed in a future version of this handbook.

Issue 368288:  Volume 1, Chapter 9, SEU Mitigation in Cyclone IV Devices, Version 1.1

Table 9-2 incorrectly states the CRC_ERROR pin is a dedicated output with optional open-drain functionality.  The CRC_ERROR pin, when used for the error detection circuitry, only functions as open-drain, it cannot drive high logic levels, and must have an external 10-KΩ pull-up resistor to an acceptable voltage to meet the receiving device requirements.

Issue 363311: Volume 3, Chapter 1, Cyclone IV Device Datasheet, Version 1.5

The Vicm specifications for the REFCLK pins are missing in table 1-21.  They are as follows:

     Vicm (AC coupled) = 1.1V /-5% 
     Vicm (DC Coupled), Min = 250mV and Max = 550mV

Resolution

Resolved Issues:

Issue 10005660: Volume 1, Chapter 1, Cyclone IV Device Family Overview, Version 1.1

Figure 1-3 was updated with correct package ordering codes for the F256 and E144 packages for Cyclone IV E devices in version 1.2. 

Issue 10005688: Volume 1, Chapter 1, Cyclone IV Device Family Overview, Version 1.1

Note (2) for Table 1-6 was updated with the correct core voltage requirement for Cyclone IV E devices in version 1.2.

Issue 10006437: Volume 2, Chapter 3, Cyclone IV Dynamic Reconfiguration, Version 1.0

Updated bit descriptions for rx_dataoutfull[31..0].

Issue 10006413: Volume 1, Chapter 8, Configuration and  Remote System Upgrades in Cyclone IV Devices, Version 1.2

Clarification added for tCF2ST1(nCONFIG high to nSTATUS high) timing.

Issue 10006558: Volume 2, Chapter 3, Cyclone IV Dynamic Reconfiguration, Version 1.0

DC Gain (rx_eqdcgain) settings updated in table 3-2.

Issue 359178: Volume 2, Chapter 1, Cyclone IV Transceiver Architecture, Version 1.0

GXB block labels updated in the PLL Input Reference Clocks in Transceiver Operation for F484 and Larger Packages figure.

Issue 364247: Volume 1, Chapter 10, JTAG Boundary-Scan Testing for Cyclone IV Devices, Version 1.1

When running boundary scan using a pre-configuration BSDL file prior to device configuration you must hold the nCONFIG pin low.

Issue 363791: Volume 1, Chapter 10, JTAG Boundary-Scan Testing for Cyclone IV Devices, Version 1.1

IDCODE values updated for EP4CGX50 and EP4CGX30 devices in the F23 package.

Issue 377866: Volume 1, Chapter 8, Configuration and Remote System Upgrades in Cyclone IV Devices, Version 1.3.

Guidelines added to avoid timing violations for Cyclone IV E devices with 1.0V core voltage in multi-device AS configuration where the slave device is configured by PS mode.

 Issue 35734: Volume 1, Chapter 6, I/O Features in the Cyclone IV Devices, Version 2.3

Page 4 describes the programmable slew rate control option and states "You cannot use the programmable slew rate feature when using OCT with calibration."  

Programmable slew rate is available when using OCT without calibration. There is no documentation error.

Related Products

This article applies to 2 products

Cyclone® IV E FPGA
Cyclone® IV GX FPGA

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