Yes, you can modify the direction of DCLK in your Cyclone® series, Stratix® series (beginning with Stratix II devices) and Arria® GX series devices BSDL file, so that you can control it during boundary scan.
The direction of DCLK depends upon the configuration mode of the FPGA,. The configuration mode is defined by the FPGA's MSEL pins which are sampled when nCONFIG goes high, either at power-up or during reconfiguration.
In PS/FPP mode, DCLK is an input. In AS mode, DCLK is an output. By default, in our BSDL files, DCLK is defined as an input.
If running in AS mode, you can modify the BSDL file such that DCLK is bidirectional so that it can be controlled during boundary scan, if required.
To do this, change the mode of DCLK from in bit to inout bit:
DCLK : inout bit;
and then edit the DCLK line as shown in the example below (BSC group and pin number will differ depending upon the device you are using):
--BSC group 177 for Family-specific input pin H4
"531 (BC_4, DCLK, input, X)," &
"532 (BC_4, *, internal, X)," &
"533 (BC_4, *, internal, X)," &
--BSC group 177 for Family-specific bidir pin H4
"531 (BC_1, DCLK, input, X)," &
"532 (BC_1, *, control, 1)," &
"533 (BC_1, DCLK, output3, X, 532, 1, Z)," &