Article ID: 000081758 Content Type: Troubleshooting Last Reviewed: 09/04/2018

Enabling Periphery to Core Placement and Routing Optimization in Arria 10 designs might cause timing violations

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Timing violations might occur when you enable the Quartus® Prime software\'s Periphery to Core Placement and Routing Optimization feature for Arria® 10 engineering sample (ES) devices.

    Resolution

    There is no workaround. This issue will be fixed in a future release of the Quartus Prime software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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