50G Interlaken IP Core Testbench Does Not Raise SOP Signal as Required

In the 50G Interlaken IP core example design, the testbench generates packets that it sends in interleaved bursts on the 50G Interlaken IP core TX user data transfer interface. Currently, the testbench sends packets without asserting the itx_sop signal at the start of a burst from a new channel. (The testbench does assert the itx_sop signal at the start of the first data burst in the input to the IP core, but not on subsequent start-of-burst cycles that should also be start-of-packet cycles). The first clock cycle of start-of-burst data from a new channel must be a start-of-packet cycle, but the input to the 50G Interlaken IP core ignores this fact.

This issue has no design impact. However, you should not design your system with the itx_sop behavior that you observe in the testbench.

This issue is fixed in version 13.0 SP1 of the 50G Interlaken MegaCore function testbench.